1. Field of the Invention
The present invention relates to a layout of a semiconductor integrated circuit including an ESD (electro-static discharge) protection circuit.
2. Description of Related Art
In semiconductor integrated circuits of recent years, an ESD protection circuit is provided between a signal input terminal and a power supply terminal or between power supply terminals to prevent electrostatic breakdown caused by externally applied static electricity.
FIGS. 8A to 8C show a conventional ESD protection circuit. FIG. 8A is a plan view, FIG. 8B is a sectional view taken along the line a-a′ and FIG. 8C is a sectional view taken along the line b-b′. The ESD protection circuit 50 shown in FIGS. 8A to 8C is a MOS protection circuit of a multifinger structure. Reference numerals 51, 52 and 53 denote a gate, a source and a drain of the ESD protection circuit 50, respectively.
Connecting wires 41, 42, 43 and 44 are arranged above the ESD protection circuit 50 and connected to the ESD protection circuit 50. The connecting wires 41, 42, 43 and 44 are formed in first, second, third and fourth metal layers, respectively, and extend along the extending direction of the source 52 and the drain 53 of the ESD protection circuit 50 (a lateral direction in FIG. 8A). Reference numerals 45 and 46 denote wires arranged between the connecting wires 41 to 44 and a pad. The wires 45 are formed in the fourth metal layer and the wire 46 is formed in a fifth metal layer.    (Patent Literature 1) Publication of Japanese Patent Application No. 2001-339047
In the conventional ESD protection circuit, the connecting wires 41 to 44 formed in the corresponding metal layers and connected to the ESD protection circuit 50 extend in the same direction as the extending direction of the source 52 and the drain 53 of the ESD protection circuit 50. Therefore, a signal wire extending in the same direction as the extending direction of the connecting wires (e.g., a signal wire 48 shown in FIG. 8A) may be arranged to run above the ESD protection circuit. However, a signal wire extending in the direction different from the extending direction of the connecting wires (e.g., a signal wire 47 shown in FIG. 8B) cannot be arranged to run above the ESD protection circuit because the connecting wires hinder the extension of the signal wire. Accordingly, the space above the ESD protection circuit cannot be freely used as a signal wire region and the signal wires have to be routed not to run above the ESD protection circuit region.
Under the circumstances, the signal wires are congested around the ESD protection circuit as shown in FIG. 9. This may bring about degradation of signal characteristics and increase of a chip area. FIG. 9 shows the ESD protection circuit and signal wires arranged around the ESD protection circuit. Referring to FIG. 9, a wire preferential direction of signal wires in an upper layer is a lateral direction, while that of signal wires in a lower layer is a longitudinal direction. Although the signal wires in the upper layer include longitudinally extending wires such as wires A, their wire preferential direction is considered as the lateral direction since most of the signal wires in the upper layer extend in the lateral direction.